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Espressif Systems /ESP32-S2 /SPI0 /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EXT_HOLD_EN)EXT_HOLD_EN 0 (DUMMY_OUT)DUMMY_OUT 0 (FADDR_DUAL)FADDR_DUAL 0 (FADDR_QUAD)FADDR_QUAD 0 (FADDR_OCT)FADDR_OCT 0 (FCMD_DUAL)FCMD_DUAL 0 (FCMD_QUAD)FCMD_QUAD 0 (FCMD_OCT)FCMD_OCT 0 (FREAD_DUAL)FREAD_DUAL 0 (FREAD_QUAD)FREAD_QUAD 0 (FREAD_OCT)FREAD_OCT 0 (Q_POL)Q_POL 0 (D_POL)D_POL 0 (WP)WP 0 (RD_BIT_ORDER)RD_BIT_ORDER 0 (WR_BIT_ORDER)WR_BIT_ORDER

Description

SPI control register

Fields

EXT_HOLD_EN

Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state.
DUMMY_OUT

In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
FADDR_DUAL

Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.
FADDR_QUAD

Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.
FADDR_OCT

Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.
FCMD_DUAL

Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.
FCMD_QUAD

Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.
FCMD_OCT

Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.
FREAD_DUAL

In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state.
FREAD_QUAD

In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state.
FREAD_OCT

In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state.
Q_POL

The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
D_POL

The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
WP

Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
RD_BIT_ORDER

In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
WR_BIT_ORDER

In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data